TABLE OF CONTENTS BOOK I
PART I
BASIC RANGE
MEASUREMENTS
USING A MECHANICAL
ROTARY CLOCK MODEL
PART II
L1 CLOCK SIGNAL
TRANSMISSION,
RECEPTION,
SYNCHRONIZATION & RANGE MEASUREMENT
WITH
MECHANICAL ROTARY
CLOCK MODELS
APPENDIX I
FUNDAMENTALS OF
CLOCKS
APPENDIX II
MECHANICAL MULTI-DIAL ROTARY CLOCKS
AND A MULTI-DIAL
MODEL GPS CLOCK
COMMENSURATE AND NON
COMMENSURATE RATES
APPENDIX III
DIFFERENTIAL GEAR
MECHANISMS
CLOCK RATE AND PHASE
DIFFERENCES
RATE AND PHASE LOCKED
DIALS
CYCLE SLIPPING
&
QUADRATURE PROCESSING
Chapter 1 Fundamental Concepts of Distance Measurement
using Synchronized Clocks
1.0 The
Fundamental Process of measuring Distance
1.1
Comments on the use of Models and the ICD-200 Document
1.2 Distance measurement by Time of Arrival
Measurement
1.3 The
physical process of Clock Synchronization
1.5 A
Simple Light Pulse Transmitter and Receiver to Measure Distance
1.6
Problems with the Simple Light Pulse Transmitter/Receiver System
1.8 A “Time Transfer” Linear Model
1.10 Time Transfer Linear Model with Receiver
Clock Not Synchronized to Clocks A and B
1.12 A
“Second” Counting Dial for the Clock (Modified TOW)
1.14 The
Subtle Problem of Delays at the Receiver
1.15 Extending Position Measurement to 3-D Space
Chapter 2 Introduction to the Global Positioning System
2.2 Physical Constants of a GPS Satellite Orbit that
passes Directly Overhead
2.3 A
Model For the GPS SV Clock System
2.4 Calculating Tbias Using one SV, User
Position Known
2.5 GPS
Time Receiver using Master Clock & the Delay term Tatm
2.6 Solving For User Position using four
Satellites
2.8 A Simplified Model of the GPS Receiver
2.9 The Receiver Reference Oscillator (RRO)
2.10 Satellite Position Information
CHAPTER 3 GPS Signal Structure and Use
3.1 A GPS SV TRANSMITTER MODEL
3.1.1
Embeded Timing in the 50Hz Data
3.3 The C/A Code in GPS receivers
3.4.1 Data Hiding and Data Modulated Carrier
Spectrum
3.5 Received Signal Power by User at Earths
Surface
3.7 GPS
Data Structure Overview
3.7.1 Using the Data to “Set”
Replica Clock Dials in the Receiver.
4.0 CHAPTER 4 SOLVING FOR SV
POSITION
4.3 Multiple Clocks , One Master Clock and One
time unit
4.3.1 The SV Clock Correction
Terms
4.3.2 The Ephemeris Time
Reference variables toe and tk
4.3.3 Ephemeris Reference Time, toe
4.3.5 Computing tk for any given “time sent”
4.3.6 Comments on the Time
Scaling of toe and tk
4.4.1 Solving the Equations for
SV Position and Speed
4.4.2 Second and Third Order Correction Terms
4.4.3 Some Comments On the Ephemeris Data and
Solving for SV position
4.4.4 Other SV Orbit Information, Almanac Data
4.6 toc SV Clock Reference Time
5.0 CHAPTER 5 SOLVING FOR USER
POSITION
5.1
Iteration vs. Direct Solution
5.3 The
Pseudo Range Equations for Four SV
5.4
Forming the Nominal Pseudo-Range
5.5 Forming the estimate of the Pseudo-Range to
each SV
5.6 Resulting Linear Equation Set
5.7
Flowchart, C code Program, Assumed Initial Position/User Clock Bias
5.10
Converting User Position to Lat/Long/Altitude from ECEF Coordinates (Spherical
Earth)
5.11
Corrections for Non Spherical Earth..
6.0 Chapter 6 GPS Receiver Hardware Fundamentals
6.1 Analog
vs. Digital GPS Receivers
6.1 Five
Fundamental Steps in the GPS Receiver Hardware
6.2 Block Diagram of Shared Signal Processing for a Single Channel
Receiver
6.2..3 Bandpass and Mixer stages up to 2nd
IF
6.3.1 The Doppler Scan/Track Subsystem
6.3.2 Second Mixer , LO2 and Doppler Scan/Track
6.3.3 Correlator and C/A Code Scan/Track Subsystem
6.4.3 Substantial time is needed to search for Code
and Doppler lock
6.4.4 Time can be reduced with prior knowledge
6.4.5 Estimate of Signal Acquisition Time
6.6 SV
Replica Clock Block Diagram
6.7.1 Recovering the Data Clock Phase (Setting The
20msec Dial)
6.7.2 Noise effects on Jitter of 50Hz Data
6.8
Recovery of the Correct Phase of the 1 Second Dial
6.10
Generating the SNAP_SHOT signal
(Receivers reference Clock)
6.11
Recording SV replica clock time at SNAP_SHOT instant
7.0 Chapter 7 Functional Implementation of a
GPS receiver
7.1.3 1st Mixer , 46MHz IF and
Filter, IF Power Splitter
7.2 Second Converter to 10.7Mhz IF
7.2.1 Mixer and VCXO removes
Doppler offset
7.2.3 10.7MHz Correlator with Crystal Filter
7.3 10.7 IF Processing using SA615
7.3.2 Correlation Detection
& Demod of Dither AM using RSSI
7.3.3 Quadrature Detection of
50Hz BPSK Data
7.3.4 Limited 10.7 IF to Frequency counter
7.4 Doppler Scan Track Subsystem
7.4.1 Frequency counter Frequency Discriminator
7.4.2 Center Frequency Control
7.4.3 Digital Doppler Loop filter
7.4.4 Level Detection & SCAN/TRAK
7.5.2 EXOR Detection of Code Error
7.5.3 Active Band Pass Filter
recovers Tau-Dither AM signal
7.5.4 Digital Filtering of Code Error Sign Bit
7.5.6 C/A code Generator, SV Replica Clock , Phase
State Counters & Latches
7.5.7 An example of a C/A code
Generator w/ Tau-Dither
7.6 Signal
Acquisition Process
7.6.2 Detecting Code or Doppler Lock and Switching
to Track
7.7.2 50Hz Data
RESET’s the divide by 20 block
8.0 Chapter 8: GPS Time and Frequency Reception
8.1 GPS Receiver in Time and Frequency, Rate
and Phase Errors
8.1.1 An Instrumentation Model of GPS Receiver
Clock Rate and Phase Measurements
8.1.2 Reported Rate and Phase Precision and Scale
8.1.3 Corrected and Uncorrected Receiver Clocks
8.1.4 Typical Receiver Reference Clock System and
Rate Error Propagation
8.2 Limits
on Estimating Receiver Clock Rate Error, Clock Mode
8.2.1 Estimating Predicted Doppler error due to User Position
Uncertainty
8.2.3 L1 Carrier Tracking Jitter and Clock Rate
Error
8.2.4 Measuring Carrier Rate, Doppler and Receiver
Clock Rate Error
8.2.5 Estimating Receiver Clock Rate Error
8.2.6 C/A Code Phase Measurements Limit Time
precision in L1 Time Transfer (Clock Mode)
8.3
Initial Estimate of GPS Time
8.4 Verifying the Veracity of Reported Receiver
Clock Rate and Phase Errors
8.5 Using
A DDS based Receiver Clock to introduce precise Rate & Phase Errors
8.6 GPS Disciplined Oscillators
8.7 A Rate Corrected DDS 5/10MHz Reference based on any 10MHz Clock
8.8 Receiver Delays in GPS Time Transfer
Chapter 9 The Zarlink 12 Channel GPS Receiver
9.1 The
Zarlink GP2015 RF Downconverter
9.1.1 Triple conversion to
4.039MHz IF
9.1.2 Digital Sampling Creates
IF@ 1.405MHz
9.1.3 GP2015/GP2021 Clock
Signals & Complex Mode
9.2
ZarLink GP2021 12-Channel Baseband Processor
9.2.1 Single Channel Block
Diagram
9.2.4 C/A Code Clock Generator
9.2.5 Prompt Channel , Early, Late and Dither
Codes
9.2.6 C/A Code Scanning
,Slewing
9.2.7 Code Phase Counter and Code Clock Phase
9.3.1 How do the 16-Bit
Accumulators work?
9.3.3 Digital Accumulators as
Integrators
9.3.4 Approximating a Digital
Accumulator as Analog Lowpass Filter.
9.4 An
Analog Model Of the Doppler Loop
9.4.1 Assume VCO is exactly
correct in Phase and Frequency
9.4.3 Doppler , Code Scan &
Threshold Detects
9.4. 4 Doppler Acquisition and
Track
9.5 Analog Model Approximates Unlocked Output Waveforms
9.5.2 Case 2 Frequency of VCO in error by 10Hz
9.5.3 Case 3 VCO frequency
Error is Zero, Small residual Phase Error
9.5.4 Getting Code Lock using
I&Q Data
9.6
Getting Frequency Discriminator Information from I/Q Processing
9.6.1 Analytic Signal
Interpretation of fd Sign Change
9.7 Cycle
Counting in the GP2021
Carrier Phase Measurements,
Turbo Rogue Receiver
Chapter
10: Carrier Phase Measurements and Turbo Rogue Receivers
10.1 A mechanical Clock Model of Carrier Phase
Range Measurement
10.1.1 Observer sees pure
Doppler and static Phase Offsets on Difference Clock Dial
10.1.2 Difference Clock Changes
Direction of Rotation when Doppler Changes Sign
10.1.3 Full Cycle Counting, Partial
Cycles and Sign Issues
10.1.4 Range Measurement using
Full & Fraction Cycles of Diff. Dial, Integrated Doppler
10.1.5 The Initial value of the
Full Cycle Counter
10.2 L1
Carrier Loop Processing
10.2.2 Loop Opened, Input
signal ( Fin ) is Constant, Loop Filter Input is Zero
10.2.3 Loop Opened, Frequency
ramp on Input Signal @ t1
10.2.4 df is
an estimate of SV acceleration with respect to receiver (on LOS)
10.2.5 Loop filter is a
weighted sum of acceleration and velocity terms
10.2.5 All Digital Baseband
Carrier Loop
10.2.6 Typical Loop Up-Date
Relationships
10.2.8 Slope of Accumulated Carrier Phase can be
Reversed ( i.e. inverted plot)
10.2.10 Accumulated Phase is
typically the total Phase
10.2.12 Units of Accumulated
Carrier Phase can be in cycles, counts, etc
10.3 Using
the L1 and L2 carrier phase dials to create a new Dial
10.4
Analysis of the Measurement and use of Total Integrated Carrier Phase F(t)
10.4.1 Analysis of Total
Integrated Carrier Phase and its Uses
10.4.2 Derivation of Total
Integrated Carrier Phase
10.4.3 Differences and Ratios
of F(t)’s
10.4.4 The Ratio of
F1(t) to F2(t)
10.4.5 Single Carrier
Difference of F(t), or DF(t)
10.4.6 Between Carrier Phase Differences, F1(t) - F2(t) ( ratios and single differences)
10.5 Time
precision and Time resolution in the Turbo Rogue Receiver
10.5.1 Disturbances to Carrier
Phase , An Overview
10.5.2 Turbo Rogue Time
Resolution
10.5.3 Turbo Rogue Time
Precision
10.5.4 Internally Generated
Phase Noise in the Turbo Rogue Receiver
10.5.5 A Base-Band Model of the
Carrier Tracking Loop with Phase Quantization Noise As the Input
10.5.6 Estimates of Timing
Jitter as seen by Carrier processing.
10.5.7 Summary Sampled Phase
Analysis for Turbo Rogue Receiver
10.6 Turbo
Rogue L1 C/A Receiver
10.6.1 A Mechanical Clock Model
of Turbo Rouge L1 C/A Channel Processing
10.6.2 A totally Coherent
design using 20.456MHz Master Oscillator
10.6.3 Residual Carrier and Code Phase measurements
10.6.4 Carrier Phase Dial and Chip Dial, Phase Rate
measurements
10.6.6 Delay or Range delay Estimate tC/A
10.6.7 Code rate is tied to
Carrier Rate
10.6.9 A Synthetic 20millsec
dial Mechanical Model and the Time Tag
10.6.10 Turbo Rogue Processor Block
Diagram
10.6.11 Down Conversion and
Sampling
10.6.13 Accumulator Start/Stop
control, Processing
10.6.14 Carrier Phase and Code
& Chip Dials
10.6.15 Absence of C/A Epoch
Signal, 20millisec and 1-sec Counters or replica Dials
10.6.17 Carrier Phase NCO
Command is extracted from Total Integrated Carrier Phase
10.6.18 Phase and Rate Steered
Carrier Phase Loop
10.6.20 Turbo Rogue Receiver
DSP Calculations, Performance Overview
10.6.21 Details of DSP Computations
performed in the GP Processor
10.6.22 The Counter Rotator term
A.2 Correlation, the Mathematical Statement
A.3 A Multiplier and Integrator for Digital
signals
A.4 Time Shifting or sliding one waveform with
respect to another
A.5 Correlation Pulse and A Delay Based
Discriminator
A.6 The
Error Voltage or Discriminator Output
A.10 Carrier Based Sliding Correlator
A.11 A Carrier Based Tau- Dither
Correlator/Desriminator
A.13 Recovery of signal with Negative SNR
APPENDIX B: PSEUDO RANDOM BINARY CODES AND THE C/A CODE
GENERATOR
B.1 What is a PRN Code generator?
B.2 A simple PRN Sequence Generator
B.5 Power Spectrum of a Carrier modulated with
C/A code
APPENDIX C: BPSK MODULATORS AND DEMODULATORS
C.1 BPSK Modulation /Demodulation Fundamentals
C.2 Phase and Amplitude Imbalance
C.3 Relative Merits of the BPSK Modulators
C.3.2 Transformer (or Balun) /Switch