A 16 KBS Full Duplex
Spread Spectrum Receiver RF Data Link

By: Dan Doberstein, President DKD Instruments

Preface to this Reprint

This article first appeared in SSS(Spread SPectrum Scene) in Oct 1992. In addition to the figures presented in that article a number of others have been included from my notes at that time. I hope that the reader finds the article interesting. I never had the time to finish all parts of this receiver but look forward to some volunteer help. It would be an excellent senior project for a interested engineering student. I offer my help for any interested. I can also provide IC's and components.

Dan Doberstein, Aug 1996

Part I, A 16KBS Spread Spectrum Full Duplex RF Data Link
This article describes a full duplex Direct Sequence RF data link using the cordless telephone chip set. Although this frequency band is not allocated for spread spectrum use it is legal at low power levels. With a couple of mixers and associated LO's it can be translated to other bands.
The system block diagram is shown in figure 1. The MC145168 and the MC3362 form the heart of the system. The MC14568 is a dual PLL that locks both the xmiter and receive LO's. The frequencies used for xmitt and receive are burnt into the internal ROM of the MC145168, in other words not change-able unless the reference frequency is altered. A table of 16 xmitt and 16 receive frequency pairs are available in the 45 to 49 mhz band.The channel select inputs are used to select a xmit/rec pair.
The MC3362 is a single chip dual conversion receiver that was designed for the cellular and cordless telephones. In this design it is used to convert the received signal to a first IF of 10.7 Mhz. and then to the 2nd IF of 455 KHz. A single tuned bandpass is used as the first IF filter. A bandwidth of about 1 mhz is needed here as the signal is still wide band at this stage, ie. rec' signal is not despread at this point. The 1 mhz BW is a Q of about 10 in the 10.7 filter, probably best obtained with a simple LC filter. The 1 Mhz BWcomes from the chip rate of approx 1 MHZ.

The 10.7 is mixed with the 10.24 MHz LO which has thespreading code impressed on it. The LO is phase modulated with the replica of the xmitt code.Assuming correlation of the receiver generated code(ie LOCK) the output of the 10.7 mixer is a despread carrier at 455 khz. This carrier will still have our biphase modulated data on it. The filter following the 455 IF is a bandpass filter with BW equal to about 12 KHz(Toko Ceramic). This is just enough to pass our data modulation stream of 16KHz. The data stream can be user data or 16KBS datafrom the CVSD audio coder/decoder chip , MC3418. The data is biphase modulated on the carrierusing exclusive OR gates. In addition to the data the spreading code is also EX-OR'ed to this datastream.

The resultant data stream then is applied to biphase modulator at xmitter. The MC3418 chip is a Continuously Variable Slope Demod/Mod . It takes speech or other analog signals and converts them to a lower bit rate serial data stream than one would get using straight ahead sampling theory, ie twice the highest freq component for sample rate. This would be about 10Khz for speech and at 8 bits/sample that works out to a 80 KBS serial data stream. The CVSD substantially reduces the data rate, some quality of reproduced signal is lost though. The chip not only provides the modulation but also the demodulation.
One of the design goals of this system was to simplify the frequency plan. This has cost as well as practical benefits. The PLL's, code clocks, and data clocks all are locked to or derived from one xtal oscillator at 10.24 MHz. Another advantage is that with clock coherence the data clock is automatically recovered once code lock is achieved. This simplifies data recovery problem considerably.

There are two code generators for each station, one for xmitt and one for receive. The receive code generator is used to correlate with the incoming signal. The 10.24 Mhz clock is divided by 10 to obtain the xmitt code clock. The rec' code generator is clocked by the Code Sync and Clock Generator circuitry. The code used for xmitt is WILL NOT be the same as for received. One code pair will be used for each station pair. The user will chose which code pair used by changing jumpers on code generators. The use of differennt xmit/rec codes helps with rejection of xmitt signal into recieve channel due to low correlation of these two signals, ie xmitt signal is spread, NOT despread, in rec channel.

The code Sync and Clock Generator circuitry provides a modulated version of the 10.24 MHZ. reference divided by 10 to give approximately 1.024 Mhz code clock for rec' code generation. The 1.024 MHz clock is modulated in such a way as to keep the receiver generated replica of the xmitters code aligned with incoming code on received signal.At the heart of the code lock circuit is the tua dither method of code tracking. The details are dicussed in the next section of this article.

Code Lock Circuitry
This section explains the code lock circuitry. The code lock systems job is to keep the receivers code locked or correlated with the transmitted code. The technique used is a modified Tau Dither system. Referring to the block diagram we see the 10.24 Mhz clock is modulated by the divide by 9/10/11 circuitry before it is passed to the code generator. The divide by 9/10/11 block serves the same purpose as a VCXO code clock in a conventional Tau Dither circuit.
The divide by 9/10/11 provides the mechanism to modulate the code clock so as to keep the receivers code locked to the transmitters. This circuit sends most of the time in the divide by 10 state. When a rate clock pulse is detected the 10.24 Mhz clock is divided by 9/11 for one cycle. The net effect is that for every rate pulse one input clock pulse is added or subtracted depending on the 9/11 input. The rate control input functions as a gain control point. The higher the rate clock frequency the higher the gain for a given ADV/RET command. Lower rate clock frequencies result in slower reaction to ADV/RET commands. Jitter during code lock will always be +/- 1/10 of a chip because of the discrete nature of the clock modulation.

Modulated code clock is sent to the code generator. The output of the code generator is split with one path passing through a delay element. The dithered code is created by toggling between the delayed and undelayed versions of the code. The rate of toggling is set by the dither clock.
The dithered code is used to phase modulate the 10.24 Mhz clock which here is used as the 2nd LO. The modulated LO is then bandpassed to bandlimit the resultant wide band signal. The LO is now mixed with the received signal which creates the 455 Khz IF. The spectrum shown for the 455 IF assumes code lock. If the codes are not locked the 455 IF would just be noise. The despread 455 IF still has the data modulation on it so its bandwidth is about 16Khz.
In addition to the data phase modulation on the 455 IF there is Amplitude Modulation induced by the dithering process. The dither induced AM is itself phase modulated via the correlation process. In order to keep the receivers code locked this AM signal must be recovered and processed to provide the error signal used to drive code misalignment to zero (+/- 1/10 chip). After bandpassing and detection we now have the desired AM component, the dither signal. A bandpass centered at the dither frequency is used to separate the dither AM signal from other AM signals which may be present on the 455 IF. The output of the band pass is hardlimited via the zero crosser and passed to the Dither Phase Detector. This process ignores the amplitude information contained in the dither signal and concerns itself only with the PHASE information. This is a simplification of the text book Tau Dither technique where both the phase and amplitude of the Dither signal are used. This is possible since the phase modulation on the dither signal contains the code advance/retard information while the amplitude of the dither signal contains the "how much" information. In short the circuit disregards the amplitude information present in the dither signal and uses just the phase information to maintain code lock. This simplification has a price in that higher SNR's are needed to maintain and obtain code lock.

It is easy to get confused here with all the modulations present. Remember the 455 Khz IF has the 16Kbs Biphase modulation on it and the dither induced AM is itself Biphase modulated. These two Biphase modulations are separate and distinct from each other and can be processed independently from each other as done here.
The phase of the dither signal is recovered by using an EXOR gate and comparing with the dither reference clock. The signal is low passed using the loop filter. The filter serves as an averager. The This filter in large part determines Lock range, Pull In range, Steady State code alignment error and the general dynamic behavior of the closed loop code tracking process. After zero crossing detection the signal is passed to the divide by 9/10/11 circuit. The signal out of the loop filter is also a measure of code clock frequency offsets between the transmitters code clock and the receivers code clock. If the offset is zero, i.e the code clocks are exactly the same frequency, the average value of the error will be exactly zero, or equivalent zero bias DC value. If the frequencies are not equal, the usual case, the error signal will have a non zero average value. Depending on the circuit you could run out of "headroom", hit your voltage rails, and break lock. This imposes a limit on the amount of code clock offset allowed between transmitter and receiver code clocks. It should be noted that the high dynamics from excessive frequency offsets can itself lead to failure to obtain or maintain lock.
We have closed the code tracking loop and only have the TRACK/SCAN switch left to explain. this switch is controlled by the carrier detect output of the MC3362. When no carrier is present the switch is set to scan which holds the 9/10/11 circuit in the RETARD position for scanning purposes. This switch ensures the searching in one direction as without it a random search caused by noise on ADV/RET control line would result.
Thats it for this month, next month we will discuss the CVSD Data Mod./Demod. and the Costas Loop Demodulator.

16KBS Full Duplex S.S. RF Data Link , Part III
This section examines the data demodulator and the audio reconstruction using the CVSD demodulator.
A Costas Loop demodulator is used to recover the data from the 455 Khz IF. Of course we must have code lock before an IF would be present. Assuming code lock the 455 KHz carrier has just the data modulation on it, the remaining dither modulation being negligible. The incoming carrier is first limited to remove any amplitude variation. Since the information is carried in the PHASE of the carrier this operation does not destroy any data information. After limiting it is split and sent to two identical phase detectors. Classic Costas loop demodulators use three, four quadrant, multipliers. This design approximates these multipliers with two phase detectors and one double balanced modulator. The Exar part XR2211 contains two phase detectors, a VCO with 0 and 90 degree ouputs, Input limiter and the Inphase limiter. The MC1496 does the chopper/modulator function. The two phase detectors compare the phase of the carrier with the VCO output, one at 0 degrees, the other at 90 degrees. Two channels are now present, the I or Inphase, and the Q or Quadrature. The Inphase channel carries the recovered data as shown in the timing diagrams.

The output of the phase detectors are lowpassed with the bandwidth approximately equal to the data rate. The inphase channel is now limited and sent to the MC1496. This limited signal is used to switch the output of the MC1496 from invert to noninvert state. Hence the chopper designation. To achieve this the MC1496 is used in its Double sideband, Suppressed carrier mode. Essentially the Inphase channel affects only the SIGN of the MC1496 output not its magnitude. The MC1496 output is then lowpased by the Loop filter and passed to the VCO control point. The loop filter serves exactly the same function as the loop filter in a standard PLL. The Loop, Inphase and Quadrature filters are all single pole RC types. The Loop filter should have a time constant of about 2 to 10 msec.
The timing waveforms show operation assuming the loop has acquired the carrier, in other words the frequency error between the VCO and the IF is zero and the phase error is small. If there is any frequency offset between the free running VCO frequency and the IF (there always is!) a small DC bias level will exist at the output of the Loop filter to correct out this constant frequency error. If this offset is to large, or changes with time i.e doppler shift caused by excessive receiver or transmitter relative movement, carrier acquisition will not be obtained or ,in the changing case, maintained. This "bias" is illustrated in waveform 6.

The CVSD demodulator is fed from the resynced data and reconstructs the audio signal from the serial bit stream. The 16KHz clock is only valid when the we have code lock condition. Without code lock the 16Khz clock will not be synchronous with the transmitted data clock. One of the primary advantages to coherent Direct sequence systems is that data clock synchronism is achieved simultaneously with code lock. The MC3417 Continuously Variable Slope Demodulator/Modulator converts the audio signal efficiently to and from a low bit rate serial data streams. It also does another important job by insuring a changing bit stream during "quiet" periods. Excessively long strings of all ones or zeros can create problems in receiver operation. Next month we finish up this design article with some thoughts on microprocessor interface for code selection ,a serial data interface and using the Fujitsu dual PLL MB1519 instead of the Motorola MC145168.

16KBS Spread Spec full duplex design

Part 4

This section dicusses a possible solution for code generation, alternative PLL and CVSD solutions. Figure XX shows the code generator block diagram. Instead of the tried and true shift register approach a 4K x 1bit piece of static RAM is used. A counter/address generator is driven by the dithered code clock which in turn generates sequential addresses which clock the code out of the RAM. This architecture allows complete code flexibility since codes can be generated by the controlling computer and downloaded to the RAM. A start address and code length word are also sent. This allows storing multiple codes in the RAM and accessing them on the fly.
Switching codes on the fly could be used to implement a two code system where acquisition is done using a short code of say 15 bits and after code lock switch to a much longer code. Longer codes increase the number of users (within limits) per channel and decrease the probability that another user will be "on" your code. The down side of longer codes is increased acquisition time especially with the sliding correlation method used here, hence the short/long code solution. It is the synchronizing of the switch between the codes that is tough! One method would be to deliberately put a small offset (in code bits) in the receiver long code wrt to the transmitted code at the moment when the codes are switched. This will temporally break lock but by forcing the receiver to search in one direction only,towards lock, you will quickly achieve lock again on the long code.

An interesting replacement for the MC3417 CVSD is the Harris CVSD chip set. The HC55536 does the demodulation operation while the HC55564 does the modulation operation. Operation from 9KBS to over 64KBS is claimed. The design replaces the analog filters used in the Motorola design with internal digital ones. This results in fewer components for a complete solution.
Another more flexible choice for the PLL is the Fujitsu MB1519. This dual PLL goes to 600 Mhz and has a user programmable divider using swallow A counter /N counter technique. A three wire serial interface is used so minimum hardware connection to computer is needed. The reference divider has only two values, 512 and 1024. This forces channel spacing of 20 Khz or 10 Khz with a 10.24 MHZ reference. By adding a divide by 2 prescaler, NEC 584, we can double our VCO max frequency to 1200 MHz. Of course at these higher frequencies we are losing image rejection with that 1st IF of 10.7 Mhz, so another IF in the receiver chain may need to be added.
Well that's it for this article, I hope you are inspired to try some of this out and at the least found it interesting reading.

List of Figures
figure 1
figure 2
figure 3
figure 4
figure 5, Code Clock Shift Circuit
figure 6
figure 7, Possible PAL Implementation

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