GPS Data Receiver

Preface to this Reprint of "A GPS Data Receiver"

This paper was originally published in the ARRL/CRRL publication "9th Computer Networking Conference 1990". It is a bit dated but still one of the best tutorial articles available to my knowledge. An appendix of FAQ's has been added to this reprint.

Most of the paper holds up even today but there is one error that I know of. In the brief section on GPS positioning I stated that the satellite system is synchronous. This is incorrect. Each satellite has its own atomic clock that is not "locked" to the others. Instead an error term is sent in the satellite data stream that gives that satellites clock error w.r.t. a "master" clock or GPS time. Once this error is included in calculations the system could be considered synchronous in a limited way.

This paper did not address the solution to the position problem only the receiving of the data stream. In investigating the position problem I have found that very few papers (read none) address the details of this calculation and measurement. In particular the rather sticky problem of ambiguous range data provided by the C/A code pulse epoch train at 1khz(for mil-type P code receivers this is a non issueas code period very long ). The problem is when measuring the pseudo ranges using the C/A code epochs one is really measuring N*T + t; where t is delay measured, T is one millisecond (1/ 1khz) and N is the integer number of T's contained in the actual range delay. This complicates the solution of already complicated position equations. In discussing this with some people in the GPS industry I was assured that this was "trivial" and obvious. Well it is not to me. I can see a few possible ways out like using the data bit at 50Hz to help in getting "N". Another possible way is to use doppler info to weed out values of N that do not work. The point is this has not been detailed, it is not trivial and probably is one of the most closely guarded techniques in commercial GPS receivers since its solution will have a substantial impact on that first position fix, the one that takes the longest. Once an initial position is known the value N for each pseudo range can be tracked and just the value of t needs to remeasured. I suspect commercial receivers use a combination of techniques to resolve the value of "N". Somebody need's to write it down.

I hope you find this paper interesting and informative. Your comments and questions are welcome.

Dan Doberstein, Aug 1996


Please click here to view GPS figures

This paper describes the construction of a Global Positioning System (GPS) single channel data receiver using the L1 carrier. A brief explanation of the GPS system is provided. The needed details of the GPS signal structure are also covered.

GPS uses Spread Spectrum techniques.It is one of the first world wide systems to implement this technology. These techniques will play an ever larger part in tomorrows communication systems.


GPS is a satellite system that can provide users with time and position information. The satellites transmit satellite position and GPS time information to receivers on the ground or in the air. Orbits are half synchronous. There will be 18 satellites in the completed system. Nine satellites are up with the remainder to be installed within two years(?). Three satellites must be in view to obtain latitude and longitude (if altitude known). Four must be in view to obtain latitude,longitude and altitude. These two scenarios assume that the user receiver does not know GPS time. If position is known then GPS time can be obtained. When the system is complete this information will be available globally, twenty four hours a day.


The GPS signal uses two carriers L1 and L2. L1 is at 1575.42 mhz. L2 is at 1227.6 mhz. Both carriers have data information on them. All satellites use the same two frequencies. How does the user receiver know which satellite it is looking at? By use of a code that is impressed on both carriers that is unique to that satellite. Two codes are used; the C/A code and the P code. L1 has both the C/A and the P code impressed on it. L2 has either the P or the C/A code impressed on it. The C/A code is a 1023 pseudo random binary sequence. This code is open to public usage and is not "classified". The P code is an extremely long pseudo random binary sequence that is not open to the public and is "classified". For thisreason the L2 signal is ignored. This paper addresses only the particulars of a L1 receiver. But the L1 signal has the P code on it too so how can you receive L1 with out knowing the P code? . It turns out that the method used for impressing the code(s)+data onto the carrier L1 allows for this provision.

Figure one is a simplified model of the satellite L1 generator. First note that all frequencies used are multiples of the 10.23 mhz reference. This is important and will be used later. We see from this diagram that the C/A code is at a 1.023 mhz rate while the P code is at a 10.23 mhz rate. The data clock is 50 hz. It is derived from detecting the all ones state (10 1's in a row) of the C/A code, this occurs once every 1023 bits so this is at a 1khz frequency, and dividing by 20. The two codes are exclusive OR'ed with the data to form the two BPSK modulating sources. The summation of these components results in a QPSK signal. Because of the 90 degree phase difference and the carrier spreading caused by the P code it is possible to build a C/A code BPSK receiver. In other words the P + DATA modulation on L1 can be ignored. That is what the receiver addressed in this paper does.

The minimum received power at the earths surface is -130dbm for a 0 db gain antenna. The satellite sends this out RH circular polarized. Due to the spreading of the C/A code the L1 signal is below the noise floor of the receiver. It can only be seen if the receiver has a copy of the C/A code to raise it "out of the mud" of the receiver noise. This process is called correlation and is at the heart of GPS receivers.

Figure 3 shows the spectrum of the L1 signal. The spectrum shows how the P code sin(x)/x envelope is below that of the C/A code sin(x)/x envelope.


The C/A code modulation is far and away the most complicating aspect of this receiver. But without it the system would not work. So what does the C/A code do for us? First and foremost it allows "multiple access", or simply the ability for all the satellites to use the same frequency(s) to send data on. Without it a receiver would see a jumble of signals from all satellites in view. Antijam. The C/A code will reduce a offending CW signal that finds its way into the receiver by approximately 35db. The C/A code allows accurate determination of the distance between the satellites and the receiver. And as previously mentioned retrieves the L1 signal from below the noise floor. So although it may seem the C/A code adds needless complication it is vital to the operation of GPS receivers.

As noted above the C/A code repeats every 1023 bits. This repetition marker decoded from the all 1's state is called a epoch. The C/A code can be generated by two ten stage shift registers with appropriate tap points. Figure two shows the two shift register and the interconnections needed. The tap points on register G2 determine a unique C/A code for each satellite. Table 1 is a list of the tap points used for each satellite. Whenever a carrier is modulated by codes such as the C/A code this is referred to as "spreading" due to the resulting increase in bandwidth. The receivers job is to remove the C/A code (despread) so as to retrieve the data modulation. When a receiver has its code lined up with a satellites code and keeps it this way it is said to have code lock. When in code lock the receivers C/A code epochs are in sync with the transmitted C/A code epochs. A very important detail regarding the C/A code and for that matter the entire GPS system is that all satellites are synchronous. In other words the C/A code epochs are all lined up for all satellites at transmission time. This fact is used to make the position measurement.


The velocity difference between the satellite and the user receiver causes a doppler shift of the L1 carrier. This is on the order of +7.0 khz to -7.0 khz. This causes some problems for the receiver. The problem stems from the low signal level of the received L1 signal. This forces a narrow IF bandwidth of approximately 1 khz to achieve a tolerable SNR. To over come the doppler the receiver must scan the possible dopplers and then once the signal falls inside the 1 Khz IF filter it must keep it there using some sort of doppler tracker. The doppler is also present on the C/A code clock of 1.023 Mhz. This is due to the coherent nature of the transmitter. The doppler on the code clock is equal to the doppler on the carrier divided by 1540, the multiplying factor between the 1575.42 Mhz carrier and the code clock at 1.023 Mhz. So for 7khz doppler on the carrier we see approximately a 7 hz doppler on the code clock. Again the receiver must be able to tolerate this offset.


Figure 1 shows that the GPS data rate is 50 bits per second. Ignoring the code modulation for the moment the data stream modulates the carrier via the BPSK modulator. Being that the content of the data stream is fairly complex, discussion of this will be postponed for now. Once the receiver removes the C/A code and has doppler lock data demodulation can take place. Any type of BPSK demodulator can be used. I used one based on a PLL but many of the designs in the literature use the Costas loop demodulator.


Although the receiver described in this paper does not make the position measurement some words on this are needed.

The key to the position measurement is the fact that all satellites are synchronous. This means that at all of the satellite transmitters the C/A code epochs are "lined up". This is indicated in figure 4. But to the user the epochs arrive at different times due to the different path lengths. Again see figure 4. These differences in path lengths are called pseudo ranges. It is the receivers job to measure these time of arrival differences w.r.t. his own clock and then compute the pseudo ranges and solve for user position and clock bias w.r.t. GPS time. This involves solving a system of four equations with four unknowns given the pseudo ranges and satellite positions from the measurements and satellite data. The equations are shown in figure 4.

The measurement of the path delays or pseudo ranges presents a problem for the single channel receiver such as the one described here. The single channel receiver must acquire and track four satellites sequentialy as opposed to a four channel receiver which can track four satellites simultaneously.

If the user knows any one of the four unknowns an equation can be eliminated. The complexity of the sequential tracking and the solution of the equations requires a computer interface and a companion program. Also needed is a high speed digital latch to measure the path delays. At this time I have not pursued the position problem.


Before anything can happen in the receiver whether its doppler tracking, data demodulation or position measurement the receiver must line up its own generated C/A code with that of the transmitted L1 signal. If the two codes are not within two "chips" of alignment there is no signal for doppler, data ect. A "chip" is the duration or length of one bit of code. This was for me the toughest problem to solve primarily because this is the one aspect of a GPS receiver that is completely different from conventional receivers. The method used to obtain code lock is the Tau-Dither circuit. This is a well documented method (but no actual circuits!) and is found in the references provided. I will leave the details of my implementation of this technique for later when the receiver hardware is discussed.


There are right now many commercially made GPS receivers on the market. I wanted to build my own receiver to 1) educate myself on receiver design, this is my first 2) Build a receiver that others could understand and if not duplicate have a good starting point 3) Be able to write this article that I hope will fill the void that currently exists in the literature on GPS and spread spectrum systems in general; a complete detailed description of an entire receiver. A benefit of this design is the fact that it is nearly all analog. Many of the commercial receivers digitize the IF and the signal disappears into a black box of digital signal processing. This is great from a cost/performance point of view but not from a intuition and learning point of view. The analog approach lends itself more to seeing the various and different trade offs in the design especially in the code tracking loop. And although the the position problem is not addressed getting the data in my opinion is the toughest nut and has the most "fruits" to be gained. The data only receiver gives excellent insights that can be applied to other spread spectrum systems.


Figure 5 shows a block diagram of the receiver. Some representative spectrums are shown at various points. The L1 signal is received using a quadrafilar circularly polarize antenna. The signal then enters a LNA. From here the signal goes through 60 feet of RG-214 (RG-213 could be used) to the crystal down converter. The down converter converts the spectrum at 1575.42 Mhz to the 1st IF of 28.644 Mhz. After passing through the 1st IF amp the signal comes to the Mixer/Correlator. This is just a DBM used in a slightly different way to achieve the 2nd IF of 5.7288 Mhz. The only difference from conventional down conversion here is that the 2nd LO is phase modulated by the receivers own C/A code generator. This is where the C/A code is removed. If the receiver generated code is lined up with the code from the satellite then the 2nd IF will be present otherwise the receiver sees only noise. Assuming the codes are locked the 2nd IF spectrum is as shown. All the LO's for the 2nd,3rd and 4th IFs are generated by division of the 114.613 Mhz VCXO. The VCXO is is needed here to compensate for doppler and is controlled by the Doppler Scan/Track circuitry. From the 2nd IF the signal goes through two more IF's to the final IF of 20 khz. This low IF is chosen so that active BPF's can be used to achieve the narrow 1 Khz bandwidths needed. At this point the signal splits three ways into the blocks Tau-Dither code tracker, Doppler Scan/Track and Data demodulator. The Phase Modulation select switch is used for providing different signals to the phase modulator for the 2nd IF LO. All except the Code w/Dither position are used for testing only.

You might be wondering where the AGC is in this design. There isn't any. The receiver runs wide open. AGC is problem due to the C/A code spreading. To have AGC it would have to become active AFTER the L1 signal is correlated which means that a switching scheme would be needed. This is not that difficult but its probably better left to a computer to decide on AGC levels. The receiver works without it so why not?


The IF's as implemented in this design are less than optimum. They came about in sort of a evolutionary way. I had some oscillators that were close, the simulator I built made some choices for me ect. The choice of the 28 mhz 1st IF was based primarily on existing designs for the ham band at 1.3 Ghz which used a 28Mhz 1st IF. Also just the abundance of circuits in the Ham literature at 28Mhz influenced me. The choice of the other IF's was based wrongly on my early attempts to make things multiples of the code clock. Not only is this not necessary you probably are asking for trouble doing this. Needless to say the design still worked and that is what counts!


The rest of this paper will be devoted to the details of the L1 receiver. I will start at the antenna and work through to the data demodulator.


The antenna is a quadrafilar type taken straight from the ARRL Antenna Book, 15th edition, pages 20-1 to 20-7. The design has good half hemisphere coverage which is exactly what is needed for a GPS receiver. The dimensions and other details of the antenna as built are given in figure 9. If you build this antenna make sure it is twisted the right way! This antenna has a gain of about 3db. It also is a fairly good match to 50 ohms.


Figure 6 shows a block diagram of the preamp. The first gain stage is a NEC Gasfet 32083. This FET has a gain of about 19db and a noise figure of 0.35 db at 1575 Mhz. The bias design of this fet was taken from The 1987 ARRL Handbook, pages 32-7. The input matching network is my own design. A lower cost FET such as the NEC NE720 or NE710 could be used here and not compromise performance. The element that must be tuned is the inductor in the input matching network. Tuning consists of deforming the turns while observing gain and noise figure. Tuning for maximum gain will also work at the expense of a slightly higher noise figure, but still acceptable performance.

Following the GasFet gain stage is a double tuned BPF. The bandwidth of this filter is approximately 40 mhz. The two air variable capacitors are tuned for max gain at 1575 Mhz. The small wires serve as a capacitor coupler between resonators. The insertion loss of this filter is about 2.5 db.

After the BPF are two gain stages using the MCL MAR-8's. These RF gain blocks are easy to use and relatively cheap. There is no tuning associated with the these two stages. These two amps combine for about 30 db of gain.

Figures 7 and 8 give the construction detail of the preamp. It is constructed on double sided G-10 board. It is one of the few places where I used printed circuit techniques. The entire circuit is mounted in a custom made aluminum box. A SMA connector is used for the antenna input and a N type for the output to the RG-214.

The overall performance of this preamp is +46 db gain with a noise figure of 1.0 db(1.6 db if tuned by gain alone). This is acceptable but it could be better. The input match to the FET needs improvement as does the BPF.


The signal from the preamp is fed via RG-214 to the down converter. The cable has 6db of loss. In reference to figure 2 the RF input from the preamp first passes through a interdigital BPF to aid in image rejection. The detail of this filter is shown in figure 10. This design is a modification of the design in the 1987 ARRL Handbook, page 32-23. The filtered RF and LO signals are applied to a MCL DBM TFM-11 to convert to the first IF of 28.644 Mhz. The IF is then passed to a tuned amplifier that has a gain of 55 db and bandwidth of 3 Mhz. The details of this amplifier are shown in figure 11.

LO generation consists of a 28.644 Mhz xtal oscillator followed by a X54 multiplier chain to achieve the LO frequency of 1546.776 Mhz. The LO has a power level of about 7 dbm. Figure 12 shows the two spectrums of the 1540 LO. One shows the harmonic content and the other close in purity. The doubler and the two triplers to 515 Mhz were built dead bug style on a 4 by 8 inch piece of two sided G10 board. Each stage was enclosed in small shield box soldered to the board with individual +15 feed thru's to minimize coupling. The filters were also enclosed in small shield boxes.

Figure 13 shows the circuits of the doubler and the two triplers with detail on filter construction. Layout follows the schematic using dead bug construction techniques. The doubler design is taken from Solid State Design For The Radio amateur P. 44. The last tripler to 1540 Mhz is done on a separate 2 by 6 piece of G10. The input is fed from the 515 tripler via RG-74. This allows the circuit path to be broken for separate tuning/testing. The 515 to 1540 tripler uses a MAR-8 for the X3, an interdigital BPF to select the third harmonic and a MAR-4 to bring the output to power up to approx. 7 dbm. The printed circuit pattern in negative is shown in figure 15. Circuit layout and detail of the interdigital filter is shown in figure 16. The interdigital filter is a modification of the design used in the 1296 Mhz transverter in the 1987 ARRL Handbook P. 32-17. The tips on construction and tuning apply but the dimensions given in figure 16 must be used. I used end covers on the filter box which are not used in the Handbook design. Figure 17B shows the xtal downconverter system.

A buffered 57.288 Mhz output is picked off the 28.644 Mhz doubler. This is used for testing but could also drive the dividers to generate the 2nd and 3rd LO's. This method would still need some sort of VCO for the 4th IF to allow for doppler tracking. If a 28.64 Mhz VCXO is substituted for the fixed xtal oscillator the 4th LO could also be generated from this oscillator. This approach would eliminate the need for the additional oscillator and allow the 28.64 VCXO to handle doppler tracking. The design used for the 10.23 code clock VCXO could be modified for this purpose.


The circuit for the oscillator is shown in figure 17A along with layout. The crystal was obtained through ICM, Oklahoma City, OK. The oscillator could benefit from a temperature controlled oven as it can drift + or - 20 HZ. This shows up as undesirable doppler which eats away at the doppler margin. Another undesirable is that this frequency is the same as the first IF. If any of the 28.644 makes it through the multiplier chain (and some does) it will appear in the 28.644 Mhz IF. This is not as bad as it would first appear. The high gain of the preamp helps here as does the C/A code which as mentioned earlier will reduce any CW by 35 db. A 57.288 Mhz oven controlled overtone oscillator would solve both problems.


The 28.644 Mhz IF is fed to a DBM (MCL SBL-1) that does the correlation and down conversion to the second IF. The correlation is performed by phase modulating the LO drive. Phase modulation is done using a DBM (MCL SBL-1) driven at the I port by the C/A code. After the phase modulation the LO is BPF to limit the spectrum. As mentioned above when the receiver generated code is lined up within two chips the code on the L1 signal the second IF will be present, otherwise noise.

The 22.9 Mhz LO is derived by dividing the 114.613 VCXO output by 10 and then filtering to get the second harmonic. This is done using the ECL counter MC10136. The details of the circuits for the 2nd,3rd,4th IF's and associated LO's is shown in figure 18.

The VCXO and the ECL dividers are mounted in a shield box. The ECL parts are super glued with legs flattened to G10 board. Connections should be short. The Pulse stretcher is used to lengthen the pulses from the MC10136. The rest of the 2nd IF generation circuitry is mounted in a small shield box. To drive the DBM phase modulator 7414 and 74128 are biased negative with respect to ground. This provides the bi-polar drive signal necessary for BI-PHASE or BPSK modulation. The rest of the circuit is fairly straight forward and layout follows schematic with "dead bug" methods of construction on G10 board.

The MRF 901's used in both the 2nd and 3rd IF's are overkill and 2N2222A's or equivalent will work fine although the bias resistors may have to be changed.


Nothing remarkable here just standard down conversion. The details are shown in figure 18. Construction is "dead bug" on G10 with the layout following the schematic. Each IF is mounted in its own shield box with SMA connectors for the inputs and outputs. The 4th IF box does not have the 20 Khz BPF inside. This is done at the C/A code Scan/Track and Doppler Scan/Track board.

114.6130 MHZ VCXO

This is the only oscillator I did not build. I used a Vectron oscillator that had a 100 Khz FM range. The frequency stability requirements of this oscillator are mild due to the fact that it is controlled by the doppler scan/track circuit. The frequency drift should be under 400 Hz. Its the "pull" range that is hard to come by. The oscillator used should be able to be pulled at least 40 Khz at 114 Mhz. This oscillator can be replaced by making the 28.644 xtal oscillator a VCXO. See above under crystal downconverter.


Figure 19 shows the block diagram of this system. The purpose of this system is to search for C/A code alignment and once found keep it there. Both functions are implemented by controlling the code clock frequency via the VCXO. The code clock VCXO is driven either by a constant voltage for Scan or a varying voltage for Track. An analog switch chooses between the two. When the switch is in Track position the system is said to be "closed loop". When in the Scan position the system is "open loop". Various waveforms and spectrums are shown accompanying the block diagram of figure 19. Some waveforms are open loop others are close loop. The open loop waveforms are marked with an asterisk.

Open Loop Operation:

In order to understand closed loop operation it is first necessary to understand open loop operation. In the open loop mode the code clock VCXO is held at a constant frequency offset from 1.023 Mhz, the zero doppler code rate. This frequency difference, about 10 Hz, causes the receiver generated code to "slip" by the code on the L1 signal. The time it takes for the two 1023 bit codes to make a complete pass is N/DF seconds; where N=1023 and DF=10hz the frequency difference between the two code clocks.

Ignoring the effect of the Dither for now lets look at what occurs as the two codes slide by each other. As the two codes slip they will come to point where they "correlate". Correlation is when the two codes are within two chips of alignment. As correlation occurs the 20 Khz IF will start to appear at the output of the BPF. Before correlation the output of the BPF is just noise. The 20 Khz IF doesn't appear all at once, rather it builds in amplitude reaching a peak when the two codes are in perfect alignment. As the two codes continue to slip the 20 Khz IF amplitude decreases until we are back to our noise output from the BPF. This process gives rise to the characteristic triangular shaped correlation pulse at the output of the Full Wave Detector. The width of this pulse is given by 2/DF, where DF is defined as above.

Now lets look at the effect of the Tau-Dither. Tau dither is used to generate a voltage that can be applied to the code clock VCXO as to keep the codes in "lock". It does this by determining which side of the correlation pulse the receiver generated code is on and how far it is from the peak point. If we know which side of the correlation pulse we are on we can determine if the receiver generated code should be advanced or retarded with respect to the received code. Knowing how far off we are tells us how far we need to move the code.

This information is generated by "dithering", or switching, between two versions of the receiver generated code. One version is delayed the other is not. The delay used here is about 1/2 microsecond or 1/2 chip. As the two codes slip through correlation the dither switching induces AM on the 20Khz IF. The frequency of of the AM is the same as dither clock frequency. The amplitude of this AM increases to a maximum and then decreases to zero when the the codes are in alignment. As the two codes continue to slip it again grows and diminishes to zero as we pass the correlation point. This "double hump" waveform can be generated by detecting the output of the dither BPF. This is shown in the block diagram but it is not used or needed in the actual circuit. At the midpoint of the double hump, at code alignment, the induced AM goes through a 180 degree phase shift. The phase shift contains the advance/retard information while the amplitude of the AM contains the "how far" information. The AM and its 180 degree phase shift at code alignment is caused by the triangular shape of the correlation pulse.

The dither induced AM is "picked off" the full wave detected 20 Khz IF with a BPF tuned to the dithering frequency. The dither AM is now multiplied by the dither clock reference. This recovers both the phase and amplitude information simultaneously. The output of the multiplier is lowpass filtered to give the "discriminator" error output. The 180 degree phase change causes a polarity reversal which produces the "S" shape discriminator output. We now have voltage whose polarity tells us whether to advance or retard our code and whose amplitude tells how much.

The low pass filter after the multiplier serves the same purpose as the loop filter in the more familiar phase locked loop. Much of the analysis of the code loop can be done using the tools from phase locked loops with slight modifications.

Closed Loop Operation:

When correlation occurs the carrier detector senses the the presence of the 20khz IF and flips the switch from Scan to Track. The code clock VCXO is now being controlled by the error voltage from the discriminator. The discriminator voltage constantly "pushes" the receiver code in the proper direction so as to keep the two codes in lock. When the discriminator output is positive the code should be advanced, or lower the VCXO frequency. Just the opposite for negative voltages. In this manner the code clock VCXO is frequency modulated to keep the codes in alignment.

Getting a feel for the code scan/track process is best done with the aid of L1 simulator. With the simulator the L1 code and the receiver code can be displayed on a two channel scope. By triggering on either the L1 or receivers code epoch that code can be made to "stand still" on the scope. The other code will move across the screen in the direction determined by the sign of the frequency difference and at the rate determined by the magnitude of the frequency difference. If the loop is held open all the open loop waveforms can be observed as the two codes slide through correlation.

If we allow the scan/track switch to operate we can observe the transient and steady state behavior of the code track process. In steady state the tracking jitter can be measured.

Seeing the movement and dynamic properties of the scan/track system on a scope is hard to beat for getting a handle on this tricky problem.


Figure 20 shows the schematic diagram of the code scan/track circuit. This is a direct implementation of the block diagram of figure 19 with the exception of the dither detection which is omitted as stated above.

20 Khz IF Detector:

This is a full wave detector. LF 356 op amps are used for there high slew rate. This circuit was taken from P. 241 of the OP Amp Cookbook by Walter Jung, 3rd ed.

Carrier Detector:

The Carrier Detector consists of a LPF/Threshold detector, 10 turn pot, retriggerable one-shot, an OR gate and a LED. The one shot/OR gate are used to debounce the threshold detector output by extending the time that the analog switch is set to "track". The LED is lit for a carrier level above threshold. Threshold is set by the 10 turn pot.

Dither Bandpass Filter:

A single op amp active filter taken from P. 154 of the Active Filter Cookbook by Don Lancaster. This circuit has a Q of about 5. Because of the low frequency of the dither signal 741 type op amps work fine here. The filter is tuned to about 200 hz. See below. Four Quadrant Multiplier/LPF:

I used the Exar 2208 multiplier though any four quadrant multiplier would work due to the low frequencies involved. The details of operation and proper connections can be found in the 1988 Exar data book. A simple RC network at the output of the multiplier serves as the loop filter. The values of R and C will greatly effect code tracking performance.

Analog Switch/Amplifier:

I used a MC14051 CMOS analog switch for the scan/track selection operation. Other switches could be used, even relays, with proper circuit modifications. This is a one-of-eight mux that is used as a SPDT switch. The other inputs are grounded. This switch can only handle plus or minus 5 volt signals. Because of this a 741 gain stage is added after the switch. The switch may be damaged if inputs exceed plus or minus 5 volts.


The C/A code loop is a feedback loop and like all such loops there are trade offs in the design. The selection of the dither clock frequency is bounded by the IF bandwidth and by the need to "measure" the code error as frequently as possible. The maximum scan rate is limited primarily by CNR which in turn is related to IF bandwidth. The remaining "jitter" on the code lock is affected by the CNR, the loop filter,IF bandwidth , dither clock frequency and dither delay.

Using a Tau-Dither type of code tracking loop reduces the correlated IF amplitude by about 1.5 db for this design. This loss gets larger for longer dither delays. Longer delays give better acquisition performance but result in more jitter.

Consequently the C/A code loop design is a trade off between the various requirements that are at odds with one another. The bibliography section lists a number of references on this topic.


There are a number of adjustments that must be done to the C/A Scan/Track loop for proper operation. The adjusting is done via ten turn pots. The schematic, figure 20, shows the location of each pot with the exception of the Dither frequency pot. With the exception of the Threshold pot all are of the miniature, screw type adjustment variety.

Dither Frequency Adjustment:

The dither BPF is not tuned but instead the dither frequency is changed to fall into the fixed pass band of the dither BPF. The dither clock is a 555 timer with a pot for frequency adjustment. The dither clock is part of the C/A code generating circuit and is shown in figure 25.

The tuning procedure is as follows: a simulated 20Khz carrier is AM modulated with the dither clock. This could be done with a 555 timer and an AND gate. The output of the 200 Hz dither BPF and the 200 Hz dither clock are displayed on a two channel scope. Change the dither clock frequency until the two waveforms are either in phase, 0 degrees, or 180 degrees out of phase. This does two things; 1) It puts the dither clock frequency in the center of the Dither BPF 2) It aligns the PHASE of the detected dither AM with that of the dither clock. This is important. It insures that the multiplication of the dither AM and the dither clock is done properly. The 0 or 180 degree alignment depends on where the dither clock is picked off; either before or after a logic inversion. Figure 22 shows the dither clock tuning setup. This brings up another point. If you are having trouble "locking" try inverting the dither clock reference to the multiplier. This will invert the error voltage polarity so that advance is now a negative error voltage and retard is now a positive voltage. Or visa versa.

Code Clock Bias Adjustment:

The code clock VCXO only responds to positive voltages. Therefore a bias is needed to allow for bipolar drive. This is provided by by summing a bias voltage with the error voltage from the multiplier. The bias voltage is set to approximately 6 vdc. This assumes the code clock VCXO is adjusted properly. To adjust the bias a good frequency counter is needed. It should be accurate to + or - 5 Hz at 10.23 Mhz. The MULTIPLIER OFFSET adjustment should be done before this adjustment.

The adjustment is done as follows; disconnect the dither reference signal and ground pin 3 on the XR2208 multiplier. This should force the output of the multiplier to zero volts. Ground the IF input also just to be on the safe side. Force the track mode by reducing the threshold adjust pot until the carrier detect LED lights. This connects the VCXO control point to the output of the bias summer. Now adjust the bias pot until the frequency of the code clock is 10.230000 Mhz.

Multiplier Offset Adjust:

This adjustment compensates for any d.c. offsets in the multiplier. Ground the multiplier inputs as detailed in the Code clock bias adjustment. Now adjust the multiplier offset pot until the voltage on pin 11 of the XR2208 multiplier is zero volts.

Threshold Adjust:

Threshold adjustment is provided by a ten turn precision pot with a vernier scale. Adjustment consists of turning the pot until the carrier detect LED just starts to flicker and then backing off a little so that the LED goes out. This must be done with the entire system up and consequently is a measure of the noise floor. This sets the level at which the system will declare that a carrier is present and correlation is assumed. The vernier scale is important. It enables reseting the threshold to various levels and monitoring any increase/decrease in the noise of the system.

20 Khz BPF adjustment:

The 20 Khz IF filter is shown in figure 23. There are three identical active BPF's; Two are used for the doppler tracker and one is for the 20 Khz IF. The center frequency of these filters is adjusted by a 10 turn pot. The adjustment of the IF filter is done at the same time as the doppler filters. The details of the IF tuning are covered in the Doppler Scan/Track section.


Figure 25 shows the schematic of the C/A code generator. This is a single code version of the generator shown in figure 2. Six 7495 four bit shift registers are used to implement the two 10 bit shift registers shown in figure 2. It is hardwired for satellite vehicle 9, tap points 3 and 10. With the addition of some exclusive or gates and switching logic other codes could be generated.

Two versions of the code are generated. One delayed, one not delayed. The delayed code is the result of feeding the on time code through eight 74L04 inverter gates. This is about a 1/2 microsecond delay or 1/2 of a chip. These two versions are switched back and forth to produce the dither code. The dither clock is a 555 timer followed by a divide by 2 for square wave output. The dither frequency adjust pot is set as described above.

In addition to the dither code three other waveforms can be used for phase modulation of the 2nd LO. The three are code clock,on time code and CW (no phase mod.). These are use for testing purposes only. The 74153 is used to select one of these modulations by the setting of S1 and S2, the phase modulation select switches.

Some method must be used to reset the generator to the all ones state. This is done by the code reset button. After being debouced by the two AND gates it is synchronized to the code clock by the D flip-flop 7474. The input to the shift register is held high by this synced pulse. This loads the register with all ones.

The C/A all ones state or epoch is generated by AND'ing all ten output bits of the 10 bit shift register. Two 4 wide 7421 AND gates and two 2 wide 7408 AND gates are used for this function. The output is a 1 Khz pulse train.


The C/A code clock is a 10.23 Mhz VCXO followed by a divide by ten to produce the 1.023 Mhz code clock. Figure 26 shows the schematic of the code clock generator. The VCXO is ovenized to reduce frequency drift. This oscillator will drift less than 2 Hz at 10.23 Mhz. VCXO pull is about 250 Hz. This range can be increased by increasing the cap in series with the MV 209 diode.

Following the oscillator is a low pass filter used to reduce the upper harmonics. A MAR 3 is used as a buffer amp and a pick off point is provided for frequency monitoring. A 74160 is used to do the divide by ten operation and the 1.023 Mhz is sent out via the 7404 inverter.

The oscillator/filter/buffer were built dead bug style on a 1 1/2 X 3 inch piece of G10. This was fitted with a tin cover. The heating resistors were epoxyed to the cover. The completed oscillator was then put in a tight fitting styrofoam box. The power,heater and 10.23 Mhz outputs were brought out of the box. RG-74 was used for the 10.23 Mhz outputs.

Heater control is provided by comparing the voltage from the LM336, a precision 2.5 volt reference, and a LM335 temperature sensor. When the divided voltage from the LM335 is below 2.5 volts the heater is turned on. When above its off. The heater is made of four 220 ohm, 1/2 watt resistors in parallel. The set temperature is controlled by the 10k ten turn pot.

Code Clock VCXO Frequency Adjustment:

Frequency can be adjusted by the control point to the tuning diode, the piston trimmer on the oscillator board and to a lesser extent the oven temperature via the ten turn pot. A good frequency counter is needed to adjust this oscillator, accurate to within a few Hz at 10.23 Mhz.

The heater must be adjusted first. Prior to applying power to the heater control adjust the Temp. Set Pot for lowest temperature, i.e. wiper at the top. Now apply power and slowly bring up temperature to about 125 F or about 3.2 vdc at the temp sensor. Once the temperature has stabilized adjust the frequency of the oscillator about 100 Hz BELOW 10.23 Mhz using the piston trimmer. It is set low to allow for the d.c. bias added to the code error signal. If the trimmer cannot bring it into tune try changing the oven temp a little and readjust piston trimmer .

If a higher code scan rate is desired set the oscillator even lower. The limit here is the total pull at the control point which as mentioned above is about 250 Hz. With this range 180 hz below should be feasible and would result in about the highest scan rate that could be used with this system.

The design for the oscillator was inspired by designs found in the 1988 ARRL Handbook. The heater control circuit came from the data sheet applications for the LM 335 sensor in the Linear Data Book from National Semiconductor.


As discussed above the narrow IF bandwidth of 1Khz and the + or - 7khz doppler on the L1 carrier make it necessary to do a doppler scan and track operation. Figure 23 shows the doppler scan/track sub-system.


The scan function is implemented by letting the 8 bit UP/DOWN counter free run with the UP/DN input held low. The counter is driven by a 1.5 sec period clock. The output of the counter is converted to analog by the DAC. This results in a sawtooth waveform with a 6 minute period coming out of the DAC. The output of the DAC is summed with a bias to account for zero doppler. This is fed to the 114.613 Mhz VCXO. In other words the L1 signal is swept through all possible doppler offsets by the VCXO until it "falls" into the doppler filters. The range of the doppler scan is determined by the voltage divider at the DAC output amp. The range as shown is about + or - 5 khz.

All three filters will have some of the signal in them since they are about 500 hz apart and have approximately 1khz bandwidths. When this condition occurs in conjunction with correlation the carrier detect circuit is tripped. This activates both code and doppler track circuits.


The output of the two doppler filters is detected and low pass filtered. The comparator subtracts these two levels to determine which filter has more of the L1 signal in it. In the track mode control of the Up/Down input of the 8 bit counter is switched to the output of the comparator. If the L1 signal is more in the lower doppler filter the comparator tells the counter to count up. If the L1 signal is more in the upper doppler filter the comparator tells the counter to count down. The output of the counter, when converted to analog by the DAC, keeps the L1 signal centered in the 20 Khz IF filter.

The two D type flip-flops are used to sync the UP/DN and Carrier Detect signals to the 2 second clock pulses. The UP/DN LED gives a visual indication of which direction the counter is going. When tracking doppler the UP/DN LED should toggle between high and low at about the 2 second clock rate. I used a Burr Brown 8 bit DAC but any 8 bit DAC should work.

Adjusting the Doppler Scan/Track Circuit

There are only two adjustments to the doppler scan/track system. Doppler zero and the doppler filters center frequency. Doppler filter adjustment:

Figure 24 shows the schematic of the active filter used for the three doppler filters. The filter is tuned via R1 a ten turn miniature pot. A signal generator or 555 timer is needed as an input for tuning the filters. The lower doppler filter is tuned to approximately 19.5 Khz. The upper doppler filter is tuned to approximately 20.5 khz.

The middle doppler filter, which is used for providing the 20 Khz IF to the code loop and data demodulator, is tuned by one of two methods. The first method uses a signal generator to find the frequency at which the comparator toggles. This is the frequency that the middle filter should be tuned to. This method will produce adequate results.

The second method uses a either a 1575.42 Mhz RF or 28.644 Mhz IF simulator. The middle filter should first be tuned by the first method so this really is the "fine" tuning part. Assuming a simulator is available connect a -40 dbm 28.644 Mhz CW signal to the 1st IF input or a -120 dbm 1575 Mhz CW signal to the preamp input. Set the phase modulation select switches to CW. This allows the CW to pass "unspread" through the system and no code lock is needed. Allow the system to track the CW signal. Using a voltmeter or scope tune the middle filter for maximum voltage or amplitude. This method closes the loop and should produce a more accurate result.

Doppler Zero:

The VCXO may not be set exactly to the frequency that would put the L1 signal in the center of the 20 Khz IF filter when L1 has zero doppler on it. A bias voltage is summed with the DAC output to compensate for this error. The VCXO does not have to be set closer than + or - 200 hz.

There are many ways to adjust the VCXO for zero doppler. The most straight forward is to use a frequency counter to measure the VCXO frequency and to adjust the bias pot accordingly. If there is no offset in the oscillator used in the downconverter then the VCXO frequency for zero doppler is 114.6130 Mhz. The voltage from the DAC must set to zero to do this adjustment. The switch on the plus input of the bias amp is used for this purpose.


The combined requirements of scanning the C/A code and doppler lead to some questions about how long it takes acquire the L1 signal. Assuming that the scan rates and bandwidths remain constant CNR is the determining factor. Larger CNR's result in shorter acquisition times while smaller CNR's lead to longer ones. For a CNR of about 20 db this system will have a average acquisition time of 5 minutes. This time could be decreased by increasing the scan rates. The code scan rate would have to be increased before the doppler scan rate can be increased. The scan rates used here are slow compared to what could be used.


A block diagram for the data demodulator is shown in figure 27. The Schematic is shown in figure 28. This design is based on a block diagram found on P. 211 of Phase Locked Loops by Roland Best.

After the C/A code is removed a 50 BPS data stream remains. This is present on the 20 Khz IF as BPSK modulation. The first step in the demodulation of this data is to hard limit the 20 Khz carrier. This removes any amplitude variation. The limited IF is now fed to a CD4046 PLL chip. The PLL responds to PHASE changes on the data with an impulse, not a pulse. The impulses occur at every phase transition. Since there are two phase transitions per data bit, one for the rising edge and one for the falling edge, there are two impulses per data bit.

The impulses can have either positive or negative polarity and can flip arbitrarily. To make all impulses have a positive polarity a fullwave rectifier is used. This is done with a couple of LF356 opamps and four diodes. This design is lifted from P. 241 of the OP Amp Cookbook by Walter Jung, 3rd edition. After rectification a non-inverting gain of 3 is used to increase the impulse amplitude.

Now a 7414 is used to clean up the impulses and bring them to TTL levels. A oneshot with a output pulse width of 8 milliseconds is used to stretch the impulse into a pulse and add some noise immunity.

The data pulse train is now divided by two in order to eliminate the two pulses per bit and to "square it up". This is done with a 7474 D-type flip-flop. The Q output is taken as the demodulated data stream. Now that we have the data signal we still need to know when to sample the data waveform. The data clock is needed.

The data clock can be reconstituted by dividing the 1Khz C/A code epochs by 20. This gives the needed 50 Hz data clock. This is done using a 74160 decade counter for the divide by ten and a 7474 for the divide by 2 to get the divide by twenty. This circuit is shown in figure 28.

The only adjustment in the data demodulator is the PLL VCO frequency. The free running frequency of the VCO should be 20 Khz, the IF frequency. Adjustment can be done when tracking a satellite. When the doppler tracker settles down and is tracking the satellite monitor pin 9 of the PLL on a scope. Now adjust the VCO frequency via the 5 kohm pot until the D.C. level on pin 9 of the PLL is about zero volts. This should insure that the free running frequency of the VCO is close to 20 Khz.

Another method is to use a signal generator to generate the 20 Khz IF. This is fed to the doppler filters and the frequency varied to find the point at which the doppler comparator toggles. Now adjust the PLL VCO as above.

The performance of the data demodulator could be better. Signals with CNRs below about 15 db will produce bit errors on the order of 1 in 600 or worse. Above this the performance is quite acceptable and good results were obtained. The detected IF level that I used as a threshold was about 2 volts.


The receiver was used to track and receive data from satellite vehicle 9. The data was taken November 23, 1989 at approximately 3:30 AM PST. The satellite passed nearly overhead at this time. this insured good signal strength. Figure 29 shows a elevation plot of satellite vehicle 9 for Nov. 23 1989 at my latitude and longitude. The afternoon occurrence was at a low elevation angle and did not provide very good data but the receiver was still able to track it.

Figure 30 shows a recording of detected IF level and VCXO control voltage from the doppler tracker for the early morning occurrence. Figure 31 shows the received data spectrum from the satellite on the 20 khz IF taken at the afternoon occurrence. The doppler plot shows the sawtooth scan until the the satellite is "locked on" by the receiver. The detected IF slowly rises as the satellite comes up. Zero Doppler is a little off due to some frequency drift in the downconverter. As the satellite goes back down the doppler increases to the point where lock is broken. This is due to the drift and the fact that I was only set up for about a + or - 5 khz range of doppler. Given more doppler range the receiver should have tracked for about another hour. Once lock is broke the doppler goes back to the scan mode and the Det. IF shows just the noise level. There is a brief "lock up" after the loss of lock but it is short lived.


The data was read using a HP3270 computer that had an eight bit input port. The clock was attached to bit zero and the data to bit 1. The data line was read on either the rising or trailing edge since it was not certain at the time which would give the best results. It turned out that the trailing edge data was the good stuff.

Figure 32 is a sample of the data. The data is sent in 30 bit words. Ten words make a subframe. There are five subframes for a full frame of data. The first 8 bits of each subframe are the same. This is the preamble. After the data was read into the computer a program was used to "hunt" for the preamble pattern. When five preambles are found that are 300 bits apart a "sync" is declared.

When the "sync" is found the program then sorts the data into 30 bit words and 10 word subframes. The subframe ID's are contained in bits 20-22 of the second word in each subframe. The subframe ID's are printed in a column at the right margin. Both the inverted and non-inverted are printed as the program did not check for data polarity which can be arbitrary. The data polarity can be determined from the preamble. The polarity of the data shown is correct and the left hand column of subframe ID's is the correct one. Of course one could also tell by the sequence, i.e. 1,2,3,4 and 5 ect., as they are sent in order. The right hand column of numbers is a count of the data bits as they where read into the computer.

The important item here is the preamble. When you see that pattern repeat every 300 bits you know you have the data! Figures 33 and 34A/B show some the internal detail of the data format. These figures were taken from the ICD-GPS-200 document.

This is as far as I have taken the data analysis. To go further requires a lot more programming and possibly computer control of the receiver.


This key document is available from the GPS program office. A letter must be sent to the address given below stating name and purpose. Unfortunately they do not have to send you a copy! Although the document IS NOT classified the program office will decide on a case by case basis if the requesting party can be "trusted" with a copy. I could get no firm commitment on the qualifications needed to get the document, although I was told that if my address was in Moscow I would not receive a copy. Strangely, they did not object to the inclusion of the C/A Code Tap Point table and the Data Frame Format figures, the very information I found to be the most difficult to obtain!

The C/A code portion of the L1 signal is for public use. The GPS system was paid for and is owned by the people of the United States. Currently there are foreign and domestic manufacturers who are profiting from C/A code receivers. If the large corporations have access to system information shouldn't the experimenter and the entrepreneur?






90009-2960 PH.(213) 643-0880


I would not have been able to build this receiver without the many fine publications provided by the HAM radio people. In particular the ARRL publications. They had examples of real circuits that worked. I would also like to thank Todd Carstenson who wrote the data capture program and provided a source of encouragement. There are many people who added bits and pieces to this endeavor, librarians, co-workers, people in industry ect. who I would also like to say thanks.


Please click here to view GPS figures


1) Satellite L1 generation model.

2) C/A Code Generator.

3) Power spectrum of L1 signal.

4) Position Measurement.

5) L1 Data Receiver block diagram.

6) Preamp block diagram and schematic.

7) Layout and Artwork for Preamp.

8) Preamp box detail.

9) Quadrafilar Antenna detail.

10) 1575.42 Mhz Interdigital BPF detail.

11) 28.644 1st IF amp schematic.

12) 1st LO power spectrums.

13) 1st LO Multiplier X2,X3 and X3, 28.6 to 515.

14) none.

15) 515 to 1546 Multiplier artwork.

16) 515 to 1546 multiplier layout and 1546 filter detail.

17A) 28.644 Mhz Crystal oscillator schematic.

17B) Downconverter connection detail.

18) 2nd,3rd and 4th LO's and IF's schematic.

19) Block diagram of C/A Code Scan/Track system.

20) C/A Code Scan/Track Schematic.

21) Active 20Khz BPF Schematic.

22) Dither Clock Tuning Setup.

23) Doppler Scan/Track circuit.

24) none.

25) C/A Code Generator with Dither Code.

26) C/A Code Clock 10.23 Mhz VCXO circuit.

27) Block Diagram of Data Demodulator.

28) Data Demodulator circuit.

29) Elevation Plot for Satellite vehicle #9, Nov. 23, 1989, Lat.=34.6', Long=-119.6'

30) Det. 20Khz IF and Doppler voltage plots for Nov. 23, 1989.

31) 20Khz IF Spectrum from Satellite Vehicle #9 , Nov. 23, 1989 at approx. 1400 PST.

32) Satellite Vehicle #9 Data for Nov. 23, 1989, 0345.

33) TLM and HOW Word Format.

34A/B) Data Frame Format.


1) C/A Code Shift Register Tap Points.



The 1987 ARRL Handbook, 64th Edition.

The ARRL Antenna Book, 15th Edition.

The ARRL Electronics Data Book, 2nd Edition.

Solid State Design for the Radio Amateur, Wes Hayward and Doug DeMaw.

QRP Notebook, Doug DeMaw, W1FB, ARRL Pub.

The Satellite Experimenter's Handbook, Martin Davidoff, ARRL Pub.

Proceedings of the 22nd Conference of the Central States VHF Society, 1988 , ARRL Pub.

VHF/UHF Manual, 4th Edition, G.R. Jessop, G6JP. Published by the Radio Society of Great Britain (RSGB).


ICD-GPS-200, Interface Control Document, Rockwell International Corp.

GPS Signal Structure and Performance Characteristics, J.J. Spliker, Jr. Journal of the Institute of Navigation, Vol. 25, No. 2, Summer 1978, P. 121-146.

A Marine Navstar GPS Receiver, Reuben E. Maine, Global Positioning System Papers, Institute of Navigation Vol. II, P. 36- 43.

A Low Cost Receiver for Land Navigation, Kai P. Yiu, Richard Crawford and Ralph Eschenbach, Global Positioning System Papers, Institute of Navigation Vol. II, P. 44-60.

All Digital GPS Receiver Mechanization, Peter Ould and Robert J. Van Wechel, Global Positioning System Papers, Institute of Navigation Vol. II, P. 25-35.

Performance/Cost Ratio Optimized for GPS Receiver Design, Ralph Eschenbach and Roger Helkey,Microwave System News (MSN),Nov. 1984, P. 43-52.

Navstar Global Positioning System Offers Unprecedented Navigational Accuracy, Robert P. Denaro, MSN, NOV. 1984, P. 54- 78.


The Delay Lock Discriminator - An Optimum Tracking Device, J.J. Spilker, Jr. and D.T. Magill, Proceedings of the IRE, September 1961, P. 1403-1416.

Delay - Lock Tracking of Binary Signals, J.J. Spliker, Jr., IEEE Transactions on Space Electronics and Telemetry, March 1963, P. 1-8.

Application of Delay - Lock Radar Techniques to Deep Space Tasks, R.B. Ward, IEEE Transactions on Space Electronics and Telemetry, June 1964, P. 49-65.

A Comparison of Binary Delay - Lock Tracking Loop Implementations, Walter J. Gill, IEEE Transactions on Aerospace and Electronic Systems, Vol. AES-2, No. 4, July 1966, P. 415-424.

Analysis of a Dithering Loop for PN code Tracking, Peter Hartmann, IEEE Transactions on Aerospace and Electronic Systems, January 1974, P. 2-9.

Double Dither Loop for Pseudonoise Code Tracking, Phillip M. Hopkins, IEEE Transactions on Aerospace and Electronic Systems, Vol. AES-13, No. 6, November 1977, P. 644-650.


Spread Spectrum Systems, Robert Dixon, 2nd edition, John Wiley and Sons, 1984. For those not familiar with spread spectrum systems read this book first.

Digital Communications and Spread Spectrum Systems, Rodger E. Ziemer and Roger L. Peterson, Macmillan Pub., 1984.

Modern Communications and Spread Spectrum, George R. Cooper and Clare D. McGillem, McGraw-Hill Inc.,1986.

Digital Communications, Satellite/Earth Station Engineering, Kamilo Feher, Prentice-Hall Inc., 1983.

Coherent Spread Spectrum Systems, J.K. Holmes, Wiley, 1982.


Microwave Transistor Amplifiers Analysis and Design, Guillermo Gonzalez, Prentice-Hall Inc., 1984.

RF Circuit Design, Chris Bowick, Howard W. Sams and Co., 1982.

Ferromagnetic Core Design and Application Handbook, Doug DeMaw, Prentice-Hall, 1981.

Communications Receivers Principles and Design, Ulrich L. Rohde and T.T.N. Bucher, McGraw-Hill Inc., 1988.

Phase Locked Loops, Roland E. Best, McGraw-Hill Inc., 1984.

IC Op-Amp Cookbook, 3rd edition, Walter G. Jung, Howard W. Sams and Co., 1986.

Active Filter Cookbook, Don Lancaster, Howard W. Sams and Co., 1975.

MECL System Design Handbook, 3rd Edition, William R. Blood Jr., Motorola Inc., 1980.

1982 Linear Databook, National Semiconductor Corp., Santa Clara, Calif.

A Handy "how to use" Guide for MAR Monolithic Drop-in Amplifiers


Q. What is a pseudo random sequence?

A. A pseudo random sequence is a stream of binary numbers, 1's and 0's that APPEAR to be random. They are not random though and after some fixed number of bits the stream repeats itself. The repeatability of these sequences makes them extremely useful especially in spread spectrum systems such as GPS. If some sort of decoding is provided to detect the start or end of the sequence an EPOCH marker is generated. These sequences can be generated by a variety of methods from clocked ROM's to shift registers. The shift register technique is employed in this design.

Q. What is BPSK?

A. BPSK stands for Binary Phase Shift Keying. It also sometimes called Bi-Phase modulation, or PSK (Phase Shift Keying). BPSK modulates the phase of a carrier by either 0 Degrees or 180 Degrees. BPSK modulators are many and varied all you need is a switch and something that produces 180 degrees of phase shift and you have a modulator. Because of this simplicity BPSK modulation finds many applications, however you pay a price at the demodulator!

Q. What is QPSK?

A. QPSK stands for Quadrature Phase Shift Keying. QPSK modulates the phase of the carrier by 45,135,225 or 315 degrees. You can make a QPSK modulator by combining two BPSK modulators that have 90 degrees phase shift between the carriers.

Q. What is Correlation?

A. Correlation has many different interpretations and can be thought of in many different ways. Correlation is also referred to as despreading or carrier reconstruction for spread spectrum type systems. In terms of spread spectrum receivers correlation is used to remove the pseudo random sequence(or code) that is impressed on the carrier via BPSK modulation for GPS. This random sequence must be removed before the data can be recovered. Correlation is the technique that is used to accomplish this. By generating an exact replica of the transmitters pseudo random sequence the receiver multiplies or mixes its version with the received RF/IF/BASEBAND signal thereby removing pseudo sequence modulation leaving just the data modulation. The only hitch here, and its a big one, is that the two codes have to be lined up exactly in time. Keeping the receivers code aligned with the transmitters code is the whole ball game for spread spectrum receivers.

Q. How can all satellites use the same frequency to transmit on?

A. Each satellite has its own unique pseudo random sequence. The receiver picks which satellite it wants to listen to by selecting the pseudo code sequence for the particular satellite and performing correlation. Only the satellite with this code will be received and for all practical purposes the other satellite signals just don't exist EVEN THOUGH they are present in the receiver! This feature of spread spectrum systems is called Code Division Multiple Access or CDMA.

Q. What does "C/A code" stand for?

A. C/A stands for Coarse Acquisition. The C/A code is used to get enough information on your position, GPS time and other data to allow correlation lock with the much longer P code. The P code has many millions of bits so the C/A code is provided to assist in the capture of the P code. The P code is a military secret and therefore useless for civilian applications. Since the C/A code provides position information the P code is ignored for civilian uses.

Q. I don't understand the Tau Dither Circuit. What is its purpose?

A. The Tau Dither circuit is the control circuit that is used to keep the receivers code locked up with the transmitters code. Without this control loop the receivers code would wander in time causing correlation to be broken and a resultant loss of carrier.

Q. Are there other methods for keeping the receivers code locked to the transmitters?

A. The Tau dither technique is just one of many techniques used for this purpose. One of the advantages of the Tau Dither technique is its simplicity believe it or not!

Q. Why is the delayed version of the phase code needed?

A. The delayed version of the code is necessary for proper operation of the Tau Dither control circuit. By switching between the delayed and undelayed versions of the code at the dither frequency, or "dithering", Amplitude modulation is induced on the received signal where previously there was none. This amplitude modulation contains the information on which way the code should be moved, either advance or retard, to keep the receivers code locked to the transmitters code.

Q. I see that after the correlation point the carrier has just the data modulation left on it, but the Tau dither circuit is demodulating a signal with phase modulation on it. Is this from the data or the code phase modulation? A. Your confusing the different phase modulations. Both the code and the data modulate the transmitted signal via a BPSK process. The Tau dither circuit INDUCES Amplitude Modulation on the carrier by its "rocking" or "dithering" between delayed and undelayed versions of the code. This induced AM is NOT transmitted it is created by the dither process inside the receiver. The AM is itself phase modulated by the shape of the correlation triangle. On one side you get an AM signal with 0 degrees phase shift on the other side you get AM with 180 degrees phase shift. It is the phase of the dither induced AM that carries the Advance/Retard information that is needed to maintain code lock. It is this bi-phase modulation the Tau dither circuit is demodulating, after appropriate AM demodulation.

A. Your observation is correct with regards to the code phase modulation being removed after the correlation point. In fact if the Tau Dither circuit is doing its job and there are no "biases" the signal after correlation will virtually be pure carrier with 50 Hz phase modulated data on it. The dither induced AM will be very small in amplitude and of virtually no consequence to the data demodulator.

Q. You mean there are THREE different bi-phase modulation processes in this receiver?

A. Precisely. The code bi-phase modulates the carrier at a 1.023 Mhz rate, the data bi-phase modulates the carrier at a 50Hz rate and finally the dither induced AM is itself bi-phased modulated.

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